Panel switch wiring

This schema is a sine wave oscillator which uses operational amplifiers working in oscillation back (positive feedback), or the oscillation output to the input. This oscillator is called Wien bridge schema is often used. The oscillator Sine wave oscillator is difficult to be done due to the distortion of the oscillation signal, different oscillator square wave, triangle wave oscillator (sawtooth).

Oscillator Sine wave Circuit Diagram




In the case of C1 = C2 = C, R = R1 = R2, giving the frequency of oscillation and can be calculated using the following formula.

Formula Sine Wave Oscillator

The example of the schema was made this time is shown below.
f = 1 / (2 x 3.14 x 10 -6 0.01 x 10 x 15 x 3)

f = 1 / (0.942 x 10 -3)

f = 1.062 x 10 3

f = 1062 Hz

The actual frequency of the schema was 900 Hz.

Most engineers will recognise the problem: Your schema needs a stable 1 or 2 MHz clock generator (in the author’s case it was for a Pong game using an old AY3-8500). A suitable crystal is not to hand so you cobble together an RC oscillator (there are plenty of diagram for such a design). Now it turns out that you don’t have exactly the right capacitor so a preset pot is add e d to allow some adjustment . Before you know it the clock schema is taking up more space on the board than you had hoped. 

Providing the application does not demand a precise clock source a tiny 8-pin microcontroller may offer a better solution to the problem. It needs no additional external components and an old ATtiny15 can be found quite cheaply. Another advantage of the solution is that clock frequency adjustment does not involve changing external components and is not subject to component tolerances. 

The microcontroller’s internal RC oscillator is already accurately calibrated to 1.6 MHz. With its inbuilt PLL, internal Timer 1 can achieve up to 25.6 MHz [2]. By configuring internal dividers the timer can output a frequency in range of roughly 50 kHz up to 12 MHz from an output pin. The difference between calculated and the actual output frequency increases at higher frequencies. A meaningful upper limit of about 2 MHz is a practical value and even at this frequency the deviation from the calculated value is about 15 %.

The schema diagram could hardly be simpler, aside from the power supply connections the output signal on pin 6 (PB1) is the only other connection necessary.The example program, written in Assembler is just 15 lines long! With a program this short comments are almost super fluous but are included for clarity. The code can be downloaded from the Elektor website [1]. 

The program only needs to initialise the timer which then runs independently of processor control to output the clock sign al . The processor can then be put into sleep mode to memory used up the remaining 99 % is free for use for other tasks if required. 

The OSCCAL register contains a calibration byte which allows some adjustment of the CPU clock. This gives a certain degree of fine tuning of the output frequency. A recommendation in the Atmel data sheet indicates that the CPU clock frequency should not be greater than 1.75 MHz otherwise timer operation cannot be guaranteed. 

The more recent ATtiny45 can be substituted for the ATtiny15. In this case the CK SEL fuses should be set to put the chip’s Timer 1 into ATtiny15- compatible mode [3]. After adjustment to the program it will now be possible to obtain a higher (or more exact) frequency from the timer, the ATtiny45’s PLL can operate up to 64 MHz.