Thursday, August 21, 2014
FET Amplifier Configurations
When using FETs as amplifiers, the input signal is applied across two terminals of the FET and the output is taken across two terminals.
Three FET amplifier configurations:
- common source,
- common gate, and
- common drain.
Common Source Amplifier
The Common Source (CS) amplifier is the FET equivalent of the common emitter transistor amplifier configuration. Like the CE amplifier, it is capable of high voltage gain. The CS amplifier has the input applied between the gate and source Terminals and the output signal taken across the drain and source terminals. Therefore, the source terminal is common to both the input and output signals.
Use of coupling capacitors CIN and COUT. Their function is to block the DC or bias current from entering the AC signal source and load resistor RL.Conversely, during AC operation they couple the AC signal source to the input of the amplifier and the resulting output to the load resistor. Bypass capacitor C1 is used to bypass the source resistor and increase the amplifiers voltage gain.
Self bias CS amplifier used previously, with the load resistance removed. Note the injection of an AC signal at the gate of the FET. With a BJT amplifier, an increase in the input signal resulted in an increase in the base current. A FET amplifier however, does not have any current flowing through the gate source junction. This is due to the reverse biased PN junction (JFETs) or the silicon dioxide insulating layer (MOSFETs).Applying an input signal has an amplitude of 2Vpk-pk. As the input signal goes more positive, the signal current flows through the gate resistor RG. This current flow develops a voltage drop across RG which equals the amplitude of the applied voltage ie VIN = VG.
With the gate voltage increasing from the quiescent condition (zero volts), the gate source voltage must be decreasing because the source voltage is a positive voltage. Remember, for an N channel JFET, VGS must be negative. A decreased or less negative VGS applied to the N channel JFET , results in the drain current increasing from the quiescent condition. Note if VGS goes more negative ie -2 V to -4 V, VGS is said to be increasing. An increasing drain current produces a larger voltage drop across the drain resistor, resulting in less voltage at the output or drain terminal. With the input signal returning to zero volts, the FET amplifier is again at the quiescent point. As the input signal goes more negative the process reverses, resulting in an increasing VGS and decreasing drain current.
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